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HV dpll4_m2x2_mul_ckfixed-factor-clock V!dpll4_m2x2_ck@d00ti,gate-clock! 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(YVdpll4_m5_ck@f40ti,divider-clock?@V3dpll4_m5x2_mul_ckti,fixed-factor-clock3>LYV4dpll4_m5x2_ck@d00ti,gate-clock4 (YVjdpll4_m6_ck@1140ti,divider-clock?@V5dpll4_m6x2_mul_ckfixed-factor-clock5V6dpll4_m6x2_ck@d00ti,gate-clock6 (V7emu_per_alwon_ckfixed-factor-clock7Vcclkout2_src_gate_ck@d70 ti,composite-no-wait-gate-clock& pV9clkout2_src_mux_ck@d70ti,composite-mux-clock&*8 pV:clkout2_src_ckti,composite-clock9:V;sys_clkout2@d70ti,divider-clock;@ plmpu_ckfixed-factor-clock<V=arm_fck@924ti,divider-clock= $emu_mpu_alwon_ckfixed-factor-clock=Vdl3_ick@a40ti,divider-clock& @V>l4_ick@a40ti,divider-clock> @V?rm_ick@c40ti,divider-clock? @gpt10_gate_fck@a00ti,composite-gate-clock  VAgpt10_mux_fck@a40ti,composite-mux-clock@ @VBgpt10_fckti,composite-clockABgpt11_gate_fck@a00ti,composite-gate-clock  VCgpt11_mux_fck@a40ti,composite-mux-clock@ @VDgpt11_fckti,composite-clockCDcore_96m_fckfixed-factor-clockEVmmchs2_fck@a00ti,wait-gate-clock Vmmchs1_fck@a00ti,wait-gate-clock Vi2c3_fck@a00ti,wait-gate-clock Vi2c2_fck@a00ti,wait-gate-clock Vi2c1_fck@a00ti,wait-gate-clock Vmcbsp5_gate_fck@a00ti,composite-gate-clock  Vmcbsp1_gate_fck@a00ti,composite-gate-clock  V core_48m_fckfixed-factor-clock0VFmcspi4_fck@a00ti,wait-gate-clockF Vmcspi3_fck@a00ti,wait-gate-clockF Vmcspi2_fck@a00ti,wait-gate-clockF Vmcspi1_fck@a00ti,wait-gate-clockF Vuart2_fck@a00ti,wait-gate-clockF Vuart1_fck@a00ti,wait-gate-clockF  Vcore_12m_fckfixed-factor-clockGVHhdq_fck@a00ti,wait-gate-clockH Vcore_l3_ickfixed-factor-clock>VIsdrc_ick@a10ti,wait-gate-clockI Vgpmc_fckfixed-factor-clockIcore_l4_ickfixed-factor-clock?VJmmchs2_ick@a10ti,omap3-interface-clockJ Vmmchs1_ick@a10ti,omap3-interface-clockJ Vhdq_ick@a10ti,omap3-interface-clockJ Vmcspi4_ick@a10ti,omap3-interface-clockJ Vmcspi3_ick@a10ti,omap3-interface-clockJ Vmcspi2_ick@a10ti,omap3-interface-clockJ Vmcspi1_ick@a10ti,omap3-interface-clockJ Vi2c3_ick@a10ti,omap3-interface-clockJ Vi2c2_ick@a10ti,omap3-interface-clockJ Vi2c1_ick@a10ti,omap3-interface-clockJ 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per_48m_fckfixed-factor-clock0VOuart3_fck@1000ti,wait-gate-clockO Vgpt2_gate_fck@1000ti,composite-gate-clockVPgpt2_mux_fck@1040ti,composite-mux-clock@@VQgpt2_fckti,composite-clockPQgpt3_gate_fck@1000ti,composite-gate-clockVRgpt3_mux_fck@1040ti,composite-mux-clock@@VSgpt3_fckti,composite-clockRSgpt4_gate_fck@1000ti,composite-gate-clockVTgpt4_mux_fck@1040ti,composite-mux-clock@@VUgpt4_fckti,composite-clockTUgpt5_gate_fck@1000ti,composite-gate-clockVVgpt5_mux_fck@1040ti,composite-mux-clock@@VWgpt5_fckti,composite-clockVWgpt6_gate_fck@1000ti,composite-gate-clockVXgpt6_mux_fck@1040ti,composite-mux-clock@@VYgpt6_fckti,composite-clockXYgpt7_gate_fck@1000ti,composite-gate-clockVZgpt7_mux_fck@1040ti,composite-mux-clock@@V[gpt7_fckti,composite-clockZ[gpt8_gate_fck@1000ti,composite-gate-clock V\gpt8_mux_fck@1040ti,composite-mux-clock@@V]gpt8_fckti,composite-clock\]gpt9_gate_fck@1000ti,composite-gate-clock V^gpt9_mux_fck@1040ti,composite-mux-clock@@V_gpt9_fckti,composite-clock^_per_32k_alwon_fckfixed-factor-clock@V`gpio6_dbck@1000ti,gate-clock`Vgpio5_dbck@1000ti,gate-clock`Vgpio4_dbck@1000ti,gate-clock`Vgpio3_dbck@1000ti,gate-clock`Vgpio2_dbck@1000ti,gate-clock` Vwdt3_fck@1000ti,wait-gate-clock` Vper_l4_ickfixed-factor-clock?Vagpio6_ick@1010ti,omap3-interface-clockaVgpio5_ick@1010ti,omap3-interface-clockaVgpio4_ick@1010ti,omap3-interface-clockaVgpio3_ick@1010ti,omap3-interface-clockaVgpio2_ick@1010ti,omap3-interface-clocka Vwdt3_ick@1010ti,omap3-interface-clocka Vuart3_ick@1010ti,omap3-interface-clocka Vuart4_ick@1010ti,omap3-interface-clockaVgpt9_ick@1010ti,omap3-interface-clocka Vgpt8_ick@1010ti,omap3-interface-clocka Vgpt7_ick@1010ti,omap3-interface-clockaVgpt6_ick@1010ti,omap3-interface-clockaVgpt5_ick@1010ti,omap3-interface-clockaVgpt4_ick@1010ti,omap3-interface-clockaVgpt3_ick@1010ti,omap3-interface-clockaVgpt2_ick@1010ti,omap3-interface-clockaVmcbsp2_ick@1010ti,omap3-interface-clockaVmcbsp3_ick@1010ti,omap3-interface-clockaVmcbsp4_ick@1010ti,omap3-interface-clockaVmcbsp2_gate_fck@1000ti,composite-gate-clockV mcbsp3_gate_fck@1000ti,composite-gate-clockVmcbsp4_gate_fck@1000ti,composite-gate-clockVemu_src_mux_ck@1140 ti,mux-clockbcd@Veemu_src_ckti,clkdm-gate-clockeVfpclk_fck@1140ti,divider-clockf@pclkx2_fck@1140ti,divider-clockf@atclk_fck@1140ti,divider-clockf@traceclk_src_fck@1140 ti,mux-clockbcd@Vgtraceclk_fck@1140ti,divider-clockg @secure_32k_fck fixed-clockVhgpt12_fckfixed-factor-clockhwdt1_fckfixed-factor-clockhsecurity_l4_ick2fixed-factor-clock?Viaes1_ick@a14ti,omap3-interface-clocki rng_ick@a14ti,omap3-interface-clocki sha11_ick@a14ti,omap3-interface-clocki des1_ick@a14ti,omap3-interface-clocki cam_mclk@f00ti,gate-clockjYcam_ick@f10!ti,omap3-no-wait-interface-clock?Vcsi2_96m_fck@f00ti,gate-clockVsecurity_l3_ickfixed-factor-clock>Vkpka_ick@a14ti,omap3-interface-clockk icr_ick@a10ti,omap3-interface-clockJ des2_ick@a10ti,omap3-interface-clockJ mspro_ick@a10ti,omap3-interface-clockJ mailboxes_ick@a10ti,omap3-interface-clockJ ssi_l4_ickfixed-factor-clock?Vrsr1_fck@c00ti,wait-gate-clock Vsr2_fck@c00ti,wait-gate-clock Vsr_l4_ickfixed-factor-clock?dpll2_fck@40ti,divider-clock&@Vldpll2_ck@4ti,omap3-dpll-clockl$@4Vmdpll2_m2_ck@44ti,divider-clockmDVniva2_ck@0ti,wait-gate-clocknVmodem_fck@a00ti,omap3-interface-clock Vsad2d_ick@a10ti,omap3-interface-clock> Vmad2d_ick@a18ti,omap3-interface-clock> Vmspro_fck@a00ti,wait-gate-clock ssi_ssr_gate_fck_3430es2@a00 ti,composite-no-wait-gate-clock Vossi_ssr_div_fck_3430es2@a40ti,composite-divider-clock @$Vpssi_ssr_fck_3430es2ti,composite-clockopVqssi_sst_fck_3430es2fixed-factor-clockqVhsotgusb_ick_3430es2@a10"ti,omap3-hsotgusb-interface-clockI Vssi_ick_3430es2@a10ti,omap3-ssi-interface-clockr Vusim_gate_fck@c00ti,composite-gate-clockE  V}sys_d2_ckfixed-factor-clockVtomap_96m_d2_fckfixed-factor-clockEVuomap_96m_d4_fckfixed-factor-clockEVvomap_96m_d8_fckfixed-factor-clockEVwomap_96m_d10_fckfixed-factor-clockE Vxdpll5_m2_d4_ckfixed-factor-clocksVydpll5_m2_d8_ckfixed-factor-clocksVzdpll5_m2_d16_ckfixed-factor-clocksV{dpll5_m2_d20_ckfixed-factor-clocksV|usim_mux_fck@c40ti,composite-mux-clock(tuvwxyz{| @V~usim_fckti,composite-clock}~usim_ick@c10ti,omap3-interface-clockN  Vdpll5_ck@d04ti,omap3-dpll-clock  $ L 4Vdpll5_m2_ck@d50ti,divider-clock PVssgx_gate_fck@b00ti,composite-gate-clock& Vcore_d3_ckfixed-factor-clock&Vcore_d4_ckfixed-factor-clock&Vcore_d6_ckfixed-factor-clock&Vomap_192m_alwon_fckfixed-factor-clock"Vcore_d2_ckfixed-factor-clock&Vsgx_mux_fck@b40ti,composite-mux-clock * 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ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-pre-es3-hsmmcH Smmc1=>txrx #default1mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0txrx  disabledmmc@480ad000ti,omap3-hsmmcH ^mmc3MNtxrx  disabledmmu@480bd400'ti,omap2-iommuH mmu_isp4Vmmu@5d000000'ti,omap2-iommu]mmu_iva  disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@Dmpu ;< Ncommontxrx^mcbsp1 txrxfck  disabledmcbsp@49022000ti,omap3-mcbspI I Dmpusidetone>?Ncommontxrxsidetone^mcbsp2mcbsp2_sidetone!"txrxfckick  disabledmcbsp@49024000ti,omap3-mcbspI@I DmpusidetoneYZNcommontxrxsidetone^mcbsp3mcbsp3_sidetonetxrxfckick  disabledmcbsp@49026000ti,omap3-mcbspI`Dmpu 67 Ncommontxrx^mcbsp4txrxfckm  disabledmcbsp@48096000ti,omap3-mcbspH `Dmpu QR Ncommontxrx^mcbsp5txrxfck  disabledsham@480c3000ti,omap3-shamshamH 0d1Erxtimer@48318000ti,omap3430-timerH1%timer1~timer@49032000ti,omap3430-timerI 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dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H Dprotophypll  disabled dss_dsi1 fcksys_clkencoder@48050800ti,omap3-rfbiH  disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH   disabled dss_vencfckportendpointsVssi-controller@48058000 ti,omap3-ssissi okHHDsysgddGNgdd_mpu+ q ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHDtxrxCDssi-port@4805b000ti,omap3-ssi-portHHDtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+9isp@480bc000 ti,omap3-ispH H |rlports+bandgap@48002524H%$ti,omap34xx-bandgapVtarget-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $Dsyscfck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $Dsyscfck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivathermal-zonescpu_thermalN regulator-vddvarioregulator-fixed yvddvariovVregulator-vdd33aregulator-fixedyvdd33avVmemory@80000000|memorygpio_keys gpio-keys#default1key_enter4enter  key_f14f1  ;key_f24f2  <key_f34f3  =key_f44f4   >key_left4left   ikey_right4right   jkey_up4up   gkey_down4down   lbacklightgpio-backlight  regulator-lcd-3v3regulator-fixedylcd_3v32Z2Z !pvVdisplaysharp,ls037v7dw014lcd 2 ? L Y eportendpointsV compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-pointscpu0-supplyinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskphandlepinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsti,bit-shiftdmasdma-namesclock-frequencyti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,low-power-stopti,lockti,low-power-bypassti,dividers#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedpinctrl-namespinctrl-0ti,use_poweroffbci3v1-supplyio-channelsio-channel-namesregulator-always-onusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplybus-widthstatus#iommu-cellsti,#tlb-entriesreg-namesinterrupt-namesti,buffer-size#sound-dai-cellsti,timer-alwonti,timer-dspti,timer-pwmti,timer-secureremote-wakeup-connectedgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addresslinux,mtd-namenand-bus-widthti,nand-ecc-optgpmc,sync-clk-pslabelmultipointnum-epsram-bitsinterface-typeusb-phypowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsti,sysc-maskpolling-delay-passivepolling-delaycoefficientsthermal-sensorsgpioslinux,codedefault-onstartup-delay-uspower-supplyenvdd-supplyenable-gpiosreset-gpiosmode-gpios