6^82h(20$rockchip,rk3036-evbrockchip,rk3036&!7Rockchip RK3036 Evaluation boardaliases=/i2c@20072000B/i2c@20056000G/i2c@2005a000L/dwmmc@1021c000R/dwmmc@10214000X/dwmmc@10218000^/serial@20060000f/serial@20064000n/serial@20068000v/spi@20074000cpuszrockchip,rk3036-smpcpu@f00cpuarm,cortex-a7 sB@@cpu@f01cpuarm,cortex-a7amba simple-buspdma@20078000arm,pl330arm,primecell @ apb_pclk arm-pmuarm,cortex-a7-pmuLMdisplay-subsystemrockchip,display-subsystem$timerarm,armv7-timer*0   Nn6oscillator fixed-clockNn6^xin24mqbus_intmem@10080000 mmio-sram   smp-sram@0rockchip,rk3066-smp-sramgpu@10090000"rockchip,rk3036-maliarm,mali-400 0~gpgpmmupp0ppmmu0@@@ buscorex disabledvop@10118000rockchip,rk3036-vop +daclk_vopdclk_vophclk_vopuvw axiahbdclk disabledportendpoint@0iommu@10118300rockchip,iommu +~vop_mmu aclkiface disabledinterrupt-controller@10139000 arm,gic-400      usb@101800002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2 otgotg*9@@  disabledusb@101c00002rockchip,rk3036-usbrockchip,rk3066-usbsnps,dwc2 otghost disabledethernet@10200000#rockchip,rk3036-emacsnps,arc-emac @ HhclkmacrefmacclkUldvrmiiokaydefault     ethernet-phy@0 dwmmc@102140000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@@N<4`<4`Dbiuciu Qreset disableddwmmc@102180000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@<4` Eswbiuciuciu-driveciu-sample Rreset disableddwmmc@1021c0000rockchip,rk3036-dw-mshcrockchip,rk3288-dw-mshc!@ N<4`<4` Guybiuciuciu-driveciu-sample rx-tx"/default Sreset disabledi2s@10220000(rockchip,rk3036-i2srockchip,rk3066-i2s"@ 3i2s_clki2s_hclkR txrxdefault disabledclock-controller@20000000rockchip,rk3036-cru Hq=#gsyscon@20008000&rockchip,rk3036-grfsysconsimple-mfd reboot-modesyscon-reboot-modeJQRB]RBkRB {RBacodec-ana@20030000 rk3036-codec @H acodec_pclkq disabledhdmi@20034000rockchip,rk3036-inno-hdmi @@ -hpclkHdefault disabledportendpoint@0timer@20044000,rockchip,rk3036-timerrockchip,rk3288-timer @   a timerpclkpwm@20050000(rockchip,rk3036-pwmrockchip,rk2928-pwm ^pwmdefault disabledpwm@20050010(rockchip,rk3036-pwmrockchip,rk2928-pwm ^pwmdefault disabledpwm@20050020(rockchip,rk3036-pwmrockchip,rk2928-pwm  ^pwmdefault disabledpwm@20050030(rockchip,rk3036-pwmrockchip,rk2928-pwm 0^pwmdefault disabledi2c@20056000(rockchip,rk3036-i2crockchip,rk3288-i2c ` i2cMdefaultokayhym8563@51haoyu,hym8563QqN^xin32ki2c@2005a000(rockchip,rk3036-i2crockchip,rk3288-i2c  i2cNdefault disabledserial@20060000&rockchip,rk3036-uartsnps,dw-apb-uart  Nn6MUbaudclkapb_pclkdefault  disabledserial@20064000&rockchip,rk3036-uartsnps,dw-apb-uart @ Nn6NVbaudclkapb_pclkdefault disabledserial@20068000&rockchip,rk3036-uartsnps,dw-apb-uart  Nn6OWbaudclkapb_pclkdefaultokayi2c@20072000(rockchip,rk3036-i2crockchip,rk3288-i2c   i2cLdefault  disabledspi@20074000rockchip,rockchip-spi @ RAapb-pclkspi_pclk  txrxdefault!"#$ disabledpinctrlrockchip,rk3036-pinctrlHgpio0@2007c000rockchip,gpio-bank  $@gpio1@20080000rockchip,gpio-bank  %Agpio2@20084000rockchip,gpio-bank @ &B pcfg_pull_default&pcfg-pull-none%pwm0pwm0-pin%pwm1pwm1-pin%pwm2pwm2-pin%pwm3pwm3-pin%sdmmcsdmmc-clk%sdmmc-cmd&sdmmc-cd&sdmmc-bus1&sdmmc-bus4@&&&&sdiosdio-bus1 &sdio-bus4@ & & &&sdio-cmd&sdio-clk %emmcemmc-clk%emmc-cmd&emmc-bus8&&&&&&&&emacemac-xfer & &&&&&&& emac-mdio  && i2c0i2c0-xfer %% i2c1i2c1-xfer %%i2c2i2c2-xfer %%i2si2s-bus`&&&&&&hdmihdmi-ctl@% % % %uart0uart0-xfer &%uart0-cts&uart0-rts%uart1uart1-xfer &%uart2uart2-xfer &%spi-pinsspi-txd&!spi-rxd&"spi-clk&#spi-cs0&$spi-cs1&memory@60000000memory`@ #address-cells#size-cellscompatibleinterrupt-parentmodeli2c0i2c1i2c2mshc0mshc1mshc2serial0serial1serial2spienable-methoddevice_typeregresetsoperating-pointsclock-latencyclocksphandlerangesinterrupts#dma-cellsarm,pl330-broken-no-flushpclock-namesinterrupt-affinityportsarm,cpu-registers-not-fw-configuredclock-frequencyclock-output-names#clock-cellsinterrupt-namesassigned-clocksassigned-clock-ratesstatusreset-namesiommusremote-endpoint#iommu-cellsinterrupt-controller#interrupt-cellsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,grfassigned-clock-parentsmax-speedphy-modepinctrl-namespinctrl-0phyphy-reset-gpiosphy-reset-durationmax-frequencyfifo-depthbus-widthcap-mmc-highspeeddefault-sample-phasedisable-wpdmasdma-namesmmc-ddr-1_8vnon-removable#reset-cellsoffsetmode-normalmode-recoverymode-bootloadermode-loader#pwm-cellsreg-shiftreg-io-widthgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pins