8(x7radxa,rockpi-n8vamrs,rk3288-vmarc-somrockchip,rk3288&7Radxa ROCK Pi N8aliases=/ethernet@ff290000G/i2c@ff650000L/i2c@ff140000Q/i2c@ff660000V/i2c@ff150000[/i2c@ff160000`/i2c@ff170000e/mmc@ff0f0000k/mmc@ff0c0000q/mmc@ff0d0000w/mmc@ff0e0000}/serial@ff180000/serial@ff190000/serial@ff690000/serial@ff1b0000/serial@ff1c0000/spi@ff110000/spi@ff120000/spi@ff130000arm-pmuarm,cortex-a12-pmu0cpusrockchip,rk3066-smpcpu@500cpuarm,cortex-a12'@5<rVcpu@501cpuarm,cortex-a12'@5<rVcpu@502cpuarm,cortex-a12'@5<rVcpu@503cpuarm,cortex-a12'@5<rVcpu-opp-tableoperating-points-v2^Vopp-126000000ip opp-216000000i p opp-312000000ip opp-408000000iQp opp-600000000i#Fp opp-696000000i)|p~opp-816000000i0,pB@opp-1008000000i<popp-1200000000iGpopp-1416000000iTfrpOopp-1512000000iZJp opp-1608000000i_"ppbus simple-bus~dma-controller@ff250000arm,pl330arm,primecell%@5 apb_pclkVdma-controller@ff600000arm,pl330arm,primecell`@5 apb_pclk disableddma-controller@ffb20000arm,pl330arm,primecell@5 apb_pclkVUreserved-memory~dma-unusable@fe000000oscillator fixed-clockn6xin24mV timerarm,armv7-timer0   n6)timer@ff810000rockchip,rk3288-timer  H 5a  pclktimerdisplay-subsystemrockchip,display-subsystem@ mmc@ff0c0000rockchip,rk3288-dw-mshcFр 5Drvbiuciuciu-driveciu-sampleT  @_resetokayku default mmc@ff0d0000rockchip,rk3288-dw-mshcFр 5Eswbiuciuciu-driveciu-sampleT ! @_reset disabledmmc@ff0e0000rockchip,rk3288-dw-mshcFр 5Ftxbiuciuciu-driveciu-sampleT "@_reset disabledmmc@ff0f0000rockchip,rk3288-dw-mshcFр 5Guybiuciuciu-driveciu-sampleT #@_resetokaykudefaultsaradc@ff100000rockchip,saradc $5I[saradcapb_pclkW _saradc-apb disabledspi@ff110000(rockchip,rk3288-spirockchip,rk3066-spi5ARspiclkapb_pclk  txrx ,default disabledspi@ff120000(rockchip,rk3288-spirockchip,rk3066-spi5BSspiclkapb_pclk txrx -default disabledspi@ff130000(rockchip,rk3288-spirockchip,rk3066-spi5CTspiclkapb_pclktxrx .default !"# disabledi2c@ff140000rockchip,rk3288-i2c >i2c5Mdefault$ disabledi2c@ff150000rockchip,rk3288-i2c ?i2c5Odefault% disabledi2c@ff160000rockchip,rk3288-i2c @i2c5Pdefault& disabledi2c@ff170000rockchip,rk3288-i2c Ai2c5Qdefault'okayVkserial@ff180000&rockchip,rk3288-uartsnps,dw-apb-uart 7 5MUbaudclkapb_pclktxrxdefault()okayserial@ff190000&rockchip,rk3288-uartsnps,dw-apb-uart 8 5NVbaudclkapb_pclktxrxdefault* disabledserial@ff690000&rockchip,rk3288-uartsnps,dw-apb-uarti 9 5OWbaudclkapb_pclkdefault+okayserial@ff1b0000&rockchip,rk3288-uartsnps,dw-apb-uart : 5PXbaudclkapb_pclktxrxdefault, disabledserial@ff1c0000&rockchip,rk3288-uartsnps,dw-apb-uart ; 5QYbaudclkapb_pclk  txrxdefault- disabledthermal-zonesreserve_thermal0>.cpu_thermald0>.tripscpu_alert0NpZpassiveV/cpu_alert1N$ZpassiveV0cpu_critN_Z criticalcooling-mapsmap0e/0jmap1e00jgpu_thermald0>.tripsgpu_alert0NpZpassiveV1gpu_critN_Z criticalcooling-mapsmap0e1 j2tsadc@ff280000rockchip,rk3288-tsadc( %5HZtsadcapb_pclk _tsadc-apbinitdefaultsleep3y435s disabledV.ethernet@ff290000rockchip,rk3288-gmac)macirqeth_wake_irq585fgc]Mstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macB _stmmacethokay6inputrgmiidefault7 'P/(8AQ \8usb@ff500000 generic-ehciP 5l9qusbokayusb@ff520000 generic-ohciR )5l9qusbokayusb@ff5400002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2T 5otg{hostl: qusb2-phyokayusb@ff5800002rockchip,rk3288-usbrockchip,rk3066-usbsnps,dwc2X 5otg{otg@@ l; qusb2-phyokayusb@ff5c0000 generic-ehci\ 5 disabledi2c@ff650000rockchip,rk3288-i2ce <i2c5Ldefault<okaypmic@1brockchip,rk808&=default>?rk808-clkout1rk808-clkout2@@@@)@5@AMY@f@sregulatorsDCDC_REG1vdd_arm q\regulator-state-memDCDC_REG2vdd_gpu P pregulator-state-memDCDC_REG3vcc_ddrregulator-state-mem DCDC_REG4vcc_io2Z2ZVregulator-state-mem 82ZLDO_REG1vcc_tp2Z2Zregulator-state-memLDO_REG2 vcca_codec2Z2Zregulator-state-mem 82ZLDO_REG3vdd_10B@B@regulator-state-mem 8B@LDO_REG4vcc_wlw@w@regulator-state-mem LDO_REG5 vccio_sdw@2ZV regulator-state-mem 82ZLDO_REG6 vdd10_lcdB@B@regulator-state-memLDO_REG7vcc_18w@w@VTregulator-state-mem 8w@LDO_REG8 vcc18_lcdw@w@regulator-state-memSWITCH_REG1vcc_sdregulator-state-memSWITCH_REG2vcc_lcdregulator-state-memi2c@ff660000rockchip,rk3288-i2cf =i2c5NdefaultA disabledpwm@ff680000rockchip,rk3288-pwmhTdefaultB5_pwmokaypwm@ff680010rockchip,rk3288-pwmhTdefaultC5_pwm disabledpwm@ff680020rockchip,rk3288-pwmh TdefaultD5_pwmokaypwm@ff680030rockchip,rk3288-pwmh0TdefaultE5_pwm disabledsram@ff700000 mmio-sramp~psmp-sram@0rockchip,rk3066-smp-sramsram@ff720000#rockchip,rk3288-pmu-srammmio-sramrpower-management@ff730000&rockchip,rk3288-pmusysconsimple-mfdsVpower-controller!rockchip,rk3288-power-controller_Ah VXpower-domain@9 5chgfdehilkj$sFGHIJKLMNpower-domain@11 5opsOPpower-domain@12 5sQpower-domain@13 5sRSreboot-modesyscon-reboot-modezRBRBRB RBsyscon@ff740000rockchip,rk3288-sgrfsyscontclock-controller@ff760000rockchip,rk3288-cruv5HAjk$#gׄeрxhрxhVsyscon@ff770000&rockchip,rk3288-grfsysconsimple-mfdwV5edp-phyrockchip,rk3288-dp-phy5h24m disabledVhio-domains"rockchip,rk3288-io-voltage-domainokayT  usbphyrockchip,rk3288-usb-phyokayusb-phy@320 5]phyclk _phy-resetV;usb-phy@33445^phyclk _phy-resetV9usb-phy@348H5_phyclk _phy-resetV:watchdog@ff800000 rockchip,rk3288-wdtsnps,dw-wdt5p O disabledsound@ff88b0000,rockchip,rk3288-spdifrockchip,rk3066-spdif(5T mclkhclkUtx 6defaultV5 disabledi2s@ff890000(rockchip,rk3288-i2srockchip,rk3066-i2s( 55Ri2s_clki2s_hclkUUtxrxdefaultW9T disabledcrypto@ff8a0000rockchip,rk3288-crypto@ 0 5}aclkhclksclkapb_pclk _crypto-rstokayiommu@ff900800rockchip,iommu@ iep_mmu5 aclkifacen disablediommu@ff914000rockchip,iommu @P isp_mmu5 aclkifacen{ disabledrga@ff920000rockchip,rk3288-rga 5jaclkhclksclkX ilm _coreaxiahbvop@ff930000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopX def _axiahbdclkYokayportV endpoint@0ZVmendpoint@1[Viendpoint@2\Vcendpoint@3]Vfiommu@ff930300rockchip,iommu  vopb_mmu5 aclkifaceX nokayVYvop@ff940000rockchip,rk3288-vop  5aclk_vopdclk_vophclk_vopX  _axiahbdclk^okayportV endpoint@0_Vnendpoint@1`Vjendpoint@2aVdendpoint@3bVgiommu@ff940300rockchip,iommu  vopl_mmu5 aclkifaceX nokayV^mipi@ff960000*rockchip,rk3288-mipi-dsisnps,dw-mipi-dsi@ 5~d refpclkX 5 disabledportsportendpoint@0cV\endpoint@1dValvds@ff96c000rockchip,rk3288-lvds@5g pclk_lvdslcdceX 5 disabledportsport@0endpoint@0fV]endpoint@1gVbdp@ff970000rockchip,rk3288-dp@ b5icdppclklhqdpX o_dp5 disabledportsport@0endpoint@0iV[endpoint@1jV`hdmi@ff980000rockchip,rk3288-dw-hdmi (5 g5hmniahbisfrcecX okaykdefaultlportsportendpoint@0mVZendpoint@1nV_video-codec@ff9a0000rockchip,rk3288-vpu   vepuvdpu5 aclkhclkoX iommu@ff9a0800rockchip,iommu vpu_mmu5 aclkifacenX Voiommu@ff9c0440rockchip,iommu @@@ o hevc_mmu5 aclkifacen disabledgpu@ffa30000#rockchip,rk3288-maliarm,mali-t760$ jobmmugpu5pX  disabledV2gpu-opp-tableoperating-points-v2Vpopp-100000000ip~opp-200000000i p~opp-300000000ipB@opp-400000000iׄpopp-600000000i#Fpqos@ffaa0000syscon VRqos@ffaa0080syscon VSqos@ffad0000syscon VGqos@ffad0100syscon VHqos@ffad0180syscon VIqos@ffad0400syscon VJqos@ffad0480syscon VKqos@ffad0500syscon VFqos@ffad0800syscon VLqos@ffad0880syscon VMqos@ffad0900syscon VNqos@ffae0000syscon VQqos@ffaf0000syscon VOqos@ffaf0080syscon VPefuse@ffb40000rockchip,rk3288-efuse 5q pclk_efusecpu-id@7cpu_leakage@17interrupt-controller@ffc01000 arm,gic-400@ @ `   Vpinctrlrockchip,rk3288-pinctrl5~gpio0@ff750000rockchip,gpio-banku Q5@V=gpio1@ff780000rockchip,gpio-bankx R5Agpio2@ff790000rockchip,gpio-banky S5Bgpio3@ff7a0000rockchip,gpio-bankz T5Cgpio4@ff7b0000rockchip,gpio-bank{ U5DV8gpio5@ff7c0000rockchip,gpio-bank| V5Egpio6@ff7d0000rockchip,gpio-bank} W5Fgpio7@ff7e0000rockchip,gpio-bank~ X5Ggpio8@ff7f0000rockchip,gpio-bank Y5Hhdmihdmi-cec-c0 qVlhdmi-cec-c7 qhdmi-ddc  qqhdmi-ddc-unwedge  rqpcfg-output-lowVrpcfg-pull-up"Vspcfg-pull-down/Vtpcfg-pull-none>Vqpcfg-pull-none-12ma>K Vwsuspendglobal-pwroff qV?ddrio-pwroff qddr0-retention sddr1-retention sedpedp-hpd  ti2c0i2c0-xfer  qqV<i2c1i2c1-xfer  qqV$i2c2i2c2-xfer   q qVAi2c3i2c3-xfer  qqV%i2c4i2c4-xfer  qqV&i2c5i2c5-xfer  qqV'i2s0i2s0-bus` qqqqqqVWlcdclcdc-ctl@ qqqqVesdmmcsdmmc-clk uV sdmmc-cmd vVsdmmc-cd sVsdmmc-bus1 ssdmmc-bus4@ vvvvVsdio0sdio0-bus1 ssdio0-bus4@ sssssdio0-cmd ssdio0-clk qsdio0-cd ssdio0-wp ssdio0-pwr ssdio0-bkpwr ssdio0-int ssdio1sdio1-bus1 ssdio1-bus4@ sssssdio1-cd ssdio1-wp ssdio1-bkpwr ssdio1-int ssdio1-cmd ssdio1-clk qsdio1-pwr  semmcemmc-clk qVemmc-cmd sVemmc-pwr  sVemmc-bus1 semmc-bus4@ ssssemmc-bus8 ssssssssVspi0spi0-clk  sVspi0-cs0  sVspi0-tx sVspi0-rx sVspi0-cs1 sspi1spi1-clk  sVspi1-cs0  sVspi1-rx sVspi1-tx sVspi2spi2-cs1 sspi2-clk sV spi2-cs0 sV#spi2-rx sV"spi2-tx  sV!uart0uart0-xfer  sqV(uart0-cts sV)uart0-rts quart1uart1-xfer  s qV*uart1-cts  suart1-rts  quart2uart2-xfer  sqV+uart3uart3-xfer  sqV,uart3-cts  suart3-rts  quart4uart4-xfer  sqV-uart4-cts  suart4-rts  qtsadcotp-pin qV3otp-out qV4pwm0pwm0-pin qVBpwm1pwm1-pin qVCpwm2pwm2-pin qVDpwm3pwm3-pin qVEgmacrgmii-pins qqqqwwwwqqq wwqqV7rmii-pins qqqqqqqqqqspdifspdif-tx  qVVpcfg-pull-none-drv-8maKVupcfg-pull-up-drv-8ma"KVvpmicpmic-int sV>vbus_hostusb1-en-oc sVyvbus_typecusb0-en-oc sVzexternal-gmac-clock fixed-clocksY@ clkin_gmacV6vcc12v-dcin-regulatorregulator-fixed vcc12v_dcinVxvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@ZxV@vbus-hostregulator-fixeddefaulty vbus_hostZ@e g=vbus-typecregulator-fixeddefaultz vbus_typecZ@e g= vccio-flash-regulatorregulator-fixed vccio_flashw@w@ZV #address-cells#size-cellscompatibleinterrupt-parentmodelethernet0i2c0i2c1i2c2i2c3i2c4i2c5mshc0mshc1mshc2mshc3serial0serial1serial2serial3serial4spi0spi1spi2interruptsinterrupt-affinityenable-methodrockchip,pmudevice_typeregresetsoperating-points-v2#cooling-cellsclock-latencyclocksdynamic-power-coefficientphandleopp-sharedopp-hzopp-microvoltranges#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclock-namesstatusclock-frequencyclock-output-names#clock-cellsarm,cpu-registers-not-fw-configuredarm,no-tick-in-suspendportsmax-frequencyfifo-depthreset-namesbus-widthcap-mmc-highspeedcap-sd-highspeeddisable-wpvqmmc-supplypinctrl-namespinctrl-0non-removablevmmc-supply#io-channel-cellsdmasdma-namesreg-shiftreg-io-widthpolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicepinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,grfrockchip,hw-tshut-tempinterrupt-namesassigned-clock-parentsclock_in_outphy-modesnps,reset-active-lowsnps,reset-delays-ustx_delayrx_delayassigned-clocksphy-supplysnps,reset-gpiophysphy-namesdr_modesnps,reset-phy-on-wakeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizerockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvddio-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-off-in-suspendregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvolt#pwm-cells#power-domain-cellspm_qosoffsetmode-normalmode-recoverymode-bootloadermode-loader#reset-cellsassigned-clock-rates#phy-cellsbb-supplyflash0-supplygpio1830-supplygpio30-supplysdcard-supply#sound-dai-cellsrockchip,playback-channelsrockchip,capture-channels#iommu-cellsrockchip,disable-mmu-resetpower-domainsiommusremote-endpointddc-i2c-businterrupt-controller#interrupt-cellsgpio-controller#gpio-cellsrockchip,pinsoutput-lowbias-pull-upbias-pull-downbias-disabledrive-strengthvin-supplyenable-active-high